The present invention relates to an optical driver which is driven by an optical signal to generate a voltage signal for the application of a test pattern signal to an IC under test, an optical output type voltage sensor which outputs its detected voltage as an optical signal for the transmission of an analog amount corresponding to a measured voltage value, and an IC testing apparatus using them.
FIG. 15 illustrates the general construction of a conventional IC testing apparatus. The IC testing apparatus in common use comprises, as depicted in FIG. 15, a test head THD, a mainframe MIN with the testing device proper stored therein, a cable KBL interconnecting them, and an auto-handler HND for feeding an IC under test 10 to the test head THD on a fully automatic basis.
The illustrated prior art example adopts a system configuration wherein: an IC socket SK is mounted on the test head THD; the IC under test 10 is held in contact with the IC socket SK for electrical connection with the mainframe MIN through the cable KBL; a test pattern signal is applied from the mainframe MIN to the IC under test 10 via the cable KBL; and a response signal of the IC under test 10 is fed via the cable KBL to the mainframe MIN; the response signal and an expectation are subjected to logical comparison in the mainframe MIN to determine whether the IC under test 10 is in normal operation, thereby conducting its quality evaluation.
In association with the test head THD there is placed the auto-handler HND which automatically transfers the IC under test 10. The auto-handler HND conducts fully automatic operations of engaging the IC under test 10 with the IC socket S, and after completion of the test, disengaging the tested IC from the IC socket SK, then classifying the tested IC 10 as nondefective or defective according to test conclusions, and putting it in the storage cabinet concerned.
Because of the necessity of automatically feeding the IC under test 10 to the test head THD by the auto-handler HND as described above, the IC testing apparatus is forced to adopt a system configuration that the test head THD is placed apart from the mainframe MIN and electrically connected thereto by the cable KBL.
FIG. 16 depicts a general configuration of an electrical system in the IC testing apparatus. In the mainframe MIN there are housed a pattern generator PG, a timing generator TG, a waveform generator FOM, a logic comparator LOG, and so forth. The pattern generator PG outputs test pattern data PGDT to the waveform generator FOM. The waveform generator FOM generates a test pattern signal PGSIG of a waveform whose H and L logic are defined by the test pattern data PGDT fed from the pattern generator PG and whose rise and fall timing of the H and L logic are defined according to timing data that is provided from the timing generator TG. The test pattern signal PGSIG is generated for each input terminal TIN of the IC under test 10, and is provided via the cable KBL and a driver 12 to every input terminal TIN of the IC under test 10.
When the IC under test 10 is, for instance, a memory, data is once written in each address of the IC under test 10 using the test pattern signal PGSIG, and then data is read out from each address to an output terminal Tout. The response signal thus read out to the output terminal Tout is decided by comparators 13A and 13B of a voltage comparator 13 as to whether it has a predetermined H logic level and a predetermined L logic level, and the decision results are sent as CP1 and CP2 to the mainframe MIN via the cable KBL.
A brief description will be given, with reference to FIGS. 17A to 17D of operations of the comparators 13A and 13B. FIG. 17A depicts the waveform of a response signal Vout of the IC under test 10 read out to the output terminal Tout. The comparators 13A and 13B are supplied with a strobe pulse STR from the mainframe MIN which is generated by the timing generator TG, and output the voltage comparison results CP1 and CPxe2x80x3 in synchronization with the strobe pulse STR.
That is, at the conclusion of an elapsed time TDRY from the start of outputting the response signal Vout to the settling of its waveform, the strobe pulse STR is applied to the comparators 13A and 13B to cause it to output the comparison results CP1 and CP2. The comparator 13A is supplied with a comparison voltage VOH that defines the normal H logic level. The comparator 13B is supplied with a comparison voltage VOL that defines the normal L logic. When the H logic of the response signal Vout is further positive than the comparison voltage VOH, the comparator 13A outputs, as a test conclusion, the H-logic comparison result CP1 that represents nondefectiveness. When the L logic of the response signal Vout is further negative than the voltage VOL that defines the normal L logic, the voltage comparator 13B outputs the H-logic comparison result CP2 that represents nondefectiveness.
The comparison results CP1 and CP2 provided from the comparators 13A and 13B are sent via the cable KBL to the mainframe MIN and are subjected to a logical comparison with an expectation pattern NPG by means of a logic comparator LOG disposed in the mainframe MIN; the quality of the IC under test 10 is decided, depending on whether a mismatch is found in the logic comparator LOG.
Incidentally, there are connected to the output terminal Tout of the IC under test 10 a terminating resistor TMR for impedance matching use and a DC power supply 14 that has a terminating voltage value VT which is determined by the specifications of the IC under test 10. FIG. 16 depicts the case where the IC under test 10 is an IC of the type having its input terminals TIN and output terminal Tout provided independently of each other, but cases are also often met with that the input terminal and the output terminal share one pin. On this account, as depicted in FIG. 18, the output of each driver DR of the driver 12 and the input terminals of the comparators 13A and 13B of the voltage comparator 13 are connected together to each input/output terminal TIO of the IC under test 10. In this instance, a terminating resistor TMR is connected in series between the output terminal of each driver and its common connection point of the comparators 13A and 13B; in a mode in which to read out of the IC under test 10 the test pattern signal (data) written therein, the driver is caused to output a terminating voltage VT, then the potential level of the voltage signal Vout, read out of the IC under test 10 in a state in which the terminating condition of the IC under test 10 is satisfied, is subjected to the comparison by the comparators 13A and 13B, and the comparison results CP1 and CP2 are sent into the mainframe MIN.
It will be understood from the above that the IC testing apparatus has a configuration wherein the test head THD and the mainframe MIN are separated from each other and are electrically connected by the cable KBL.
Incidentally, users of IC testing apparatus call for testing quantities of ICs in a short time. To meet this requirement, the auto-handler HND and the test head THD are forced to become large-scale and bulky, and consequently, the length of the cable KBL is on the increase.
With an increase in the length of the longer the cable KBL, electro-magnetically induced noise becomes more likely to get mixed in the signal transmitted over the cable and the signal also becomes more susceptible to a parasitic stray capacitance and a parasitic inductor of the cable KBLxe2x80x94this imposes limitations on the transmission rate (frequency) of signals that can be transmitted between the mainframe MIN and the test head THD; that is, the lengthening of the cable leads to the disadvantage of setting limits on high-speed IC testing. This is an insuperably serious obstacle associated with the use of the configuration that interconnects the test head THD and the mainframe MIN by all electrical transnmission line.
Another problem y arises from the construction that large quantities of electronic circuit elements such as the drivers 12 and the voltage comparators 13 are housed in the narrow space of the test head THD. And there is the recent trend that the number of ICs to be tested at a time increases to 16, 32 and 64. As the number of ICs to be tested at a time increases, the calorific value per unit space in the test head THD increases and temperature also rises remarkablyxe2x80x94this requires devising a method for heat radiation and involves additional costs therefor.
A first object of the present invention is to propose an IC testing apparatus which permits dramatic improvements in the test speed, and an optical output type voltage sensor and an optical driver that are used to implement the IC testing apparatus.
A second object of the present invention is to propose an IC testing apparatus which reduces the calorific value in the test head and hence avoids the expenditure for heat radiation, and an optical output type voltage sensor and an optical driver that are used to implement the IC testing apparatus.
The present invention proposes an optical driver which interconnects the test head and the mainframe by an optical waveguide and sends a test pattern signal as an optical signal to the test head for applying the test pattern signal to the IC under test after conversion to an electric signal, and an optical output type voltage sensor which converts the response signal from the IC under test to an optical signal and sends the optical signal to the mainframe, and further proposes an IC testing apparatus using the optical driver and the optical output type voltage sensor.
Thus, according to the present invention, the test head and the mainframe are interconnected by an optical waveguide. The optical waveguide is free from the possibility of an electro-magnetically induced noise or similar electrical noise getting mixed thereinto. Further, since there is no influence of an electrostatic capacitance or parasitic inductor even if the optical waveguide is long, the frequency of the signal that is transmitted over the optical waveguide can make a dramatic leap upward as compared with the signal frequency in the IC testing apparatus using the electrical transmission line. Therefore, it is possible to realize the IC testing apparatus capable of high-speed testing.